The present invention relates to semiconductor design technology, and more particularly, to a semiconductor memory device for synchronizing a signal inputted from an external source with a clock signal and latching the synchronized signal, and a method for operating the semiconductor memory device.
In general, a semiconductor memory device such as a double data rate synchronous DRAM (DDR SRAM) receives an address signal, a data signal, and an external command signal outputted from a central processing unit (CPU) and performs desired operations based on the above signals. At this time, the semiconductor memory device synchronizes the above signals with a clock signal and latches the synchronized signals therein. Setup and hold times should be secured between the clock signal and the signals to be synchronized with the clock signal and, specially, the setup time is an important factor in the synchronization.
FIG. 1 illustrates a circuit diagram of a conventional semiconductor memory device.
Referring to FIG. 1, the semiconductor memory device includes a clock buffering unit 110, a synchronization clock generating unit 130, a plurality of signal input units 150, a plurality of delay units 170 and a plurality of latching units 190.
The clock buffering unit 110 buffers an external clock signal CLK_EXT to generate a source clock signal CLK_SRC. The synchronization clock generating unit 130 generates a synchronization clock signal CLK_SYN based on the source clock signal CLK_SRC.
The plurality of signal input units 150 receive a plurality of input signals provided from the external. First to third signal input units 150_1 to 150_3 receive first to third input signals IN1 to IN3, respectively. For the simplicity of explanation, FIG. 1 only illustrates the first to the third signal input units 150_1 to 150_3 and circuits connected to the signal input units 150, which have configurations corresponding to the first to the third signal input units 150_1 to 150_3. Herein, the first to the third input signals IN1 to IN3 are signals that are inputted through corresponding pads (not shown for the simplicity of explanation). Generally, the first to the third signal input units 150_1 to 150_3 are designed to be disposed close to the corresponding pads, respectively.
The plurality of delay units 170 delay output signals of the first to the third signal input units 150_1 to 150_3 for a predetermined delay time to thereby output delayed signals. Thus, the plurality of delay units 170 includes first to third delay units 170_1 to 170_3. Delay times reflected to the first to the third delay units 170_1 to 170_3 are determined by considering setup times between the synchronization clock signal CLK_SYN and the first to the third input signals IN1 to IN3. This will be described later in detail with reference to an operation of the semiconductor memory device.
The plurality of latching units 190 synchronize output signals of the first to the third delay units 170_1 to 170_3 with the synchronization clock signal CLK_SYN and latch the synchronized signals, thereby outputting first to third output signals OUT1 to OUT3. For the purpose, the latching units 190 include first to third latching units 190_1 to 190_3. Configuration and operation of the first to the third latching units 190_1 to 190_3 are apparent to those skilled in the art and thus explanation for the configuration and operation of the latching unit is omitted.
Hereinafter, the operation of the semiconductor memory device illustrated in FIG. 1 is described.
First of all, the external clock CLK_EXT is outputted as the synchronization clock signal CLK_SYN via the clock buffering unit 110 and the synchronization clock generating unit 130. The synchronization clock signal CLK_SYN is inputted to the first to the third latching units 190_1 to 190_3 almost simultaneously.
Meanwhile, the first to the third signal input units 150_1 to 150_3 respectively compare the first to the third input signals IN1 to IN3 inputted through the plurality of pads (not shown) with an internal reference voltage V_REF and output compared results. For instance, if the first input signal IN1 has a voltage level higher than that of the internal reference voltage V_REF, the first signal input unit 150_1 outputs a logic high signal. On the other hand, if the first input signal IN1 has a voltage level lower than that of the internal reference voltage V_REF, the first signal input unit 150_1 outputs a logic low signal. For the reference, a clock enable signal CKEb is a signal that is used to prevent current consumption from being caused by unnecessary operations in the semiconductor memory device. Therefore, the clock enable signal CKEb controls activation or inactivation of the first to the third signal input units 150_1 to 150_3.
Then, output signals of the first to the third signal input units 150_1 to 150_3 are delayed in the first to the third delay units 170_1 to 170_3 by the delay times reflected to the first to the third delay units 170_1 to 170_3, respectively. The delayed signals are transferred to the first to the third latching units 190_1 to 190_3. While the first to the third signal input units 150_1 to 150_3 are disposed close to the corresponding pads, the first to the third latching units 190_1 to 190_3 gather on one place. Therefore, if the first to the third delay units 170_1 to 170_3 are not employed in the semiconductor memory device, the output signals of the first to the third signal input units 150_1 to 150_3 may be transferred to the first to the third latching units 190_1 to 190_3 at different points of time. That is, it is impossible to secure stable setup times between the synchronization clock signal CLK_SYN and the output signals transferred from the first to the third signal input units 150_1 to 150_3 to the first to the third latching units 190_1 to 190_3.
Therefore, in order to secure the setup times, the first to the third delay units 170_1 to 170_3 provide different delay times to the output signals of the first to the third signal input units 150_1 to 150_3 and output the delayed signals generated by reflecting the different delay times. As a result, the first to the third latching units 190_1 to 190_3 receive data at the same points of time. The first to the third latching units 190_1 to 190_3 output the first to the third output signals OUT1 to OUT3 in response to the synchronization clock signal CLK_SYN and the output signals of the first to the third delay units 170_1 to 170_3 whose setup times are secured.
Referring back to FIG. 1, the first to the third delay units 170_1 to 170_3 include a plurality of inverters. The first delay unit 170_1 includes 6 inverters 170_1a to 170_1f; the second delay unit 170_2 includes 4 inverters 170_2a to 170_2d; and the third delay unit 170_3 includes 2 inverters 170_3a and 170_3b. The reason why the first to the third delay units 170_1 to 170_3 include different numbers of inverters therein is that signal transmission times between the first to the third signal input units 150_1 to 150_3 and the first to the third latching units 190_1 to 190_3 are different from each other as described above. Thus, by considering the signal transmission times measured between the signal input units and their corresponding latching units in a state of omitting the delay units, the first delay unit 170_1 having the longest delay time is disposed between the first signal input unit 150_1 and the first latching unit 190_1, which have the shortest signal transmission time there between compared to signal transmission times between the signal input units 150_2 and 150_3 and their corresponding latching units 190_2 and 190_3 described in FIG. 1.
The semiconductor memory device is developing in a direction of implementing a high-speed and low-power architecture. Specially, in order to achieve the high-speed architecture, the semiconductor memory device is designed to receive a number of data simultaneously. This means that the semiconductor memory device has to include a lot of pads. Therefore, the signal transmission time between the signal input unit and the corresponding latching unit also becomes longer and thus the number of inverters constructing the delay unit is also increased. Herein, the inverters constructing the delay unit consume switching current during transferring signals and thus the switching current consumed by the inverters is increased as the number of inverters is increased. That is, in the conventional semiconductor memory device, as the number of pads is increased, the switching current is also increased and thus the increased switching current disturbs the low-power implementation of the semiconductor memory device.